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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES Integrated front End for Single Pair or Two Pair HDSL Systems Meets ETSI Specifications Supports 1168 kbps and 2.32 Mbps Programmable Filtering Supports Adaptive HDSL Transmit and Receive Signal Path Functions Receive Hybrid Amplifier, PGA, ADC and Adaptable Filter Transmit DAC, Adaptable Filter and Differential Outputs Normal Loopback Serial Interface to Digital Transceivers Single 3 V Power Supply
2 Pair/1 Pair ETSI Compatible HDSL Analog Front End AD5011
GENERAL DESCRIPTION
The AD5011 is an analog front end for two pair or single pair HDSL applications that use 1168 kbps or 2.32 Mbps data rates. The device integrates all the transmit and receive functional blocks. A standard serial interface is used to communicate with the DAC and ADC. The filters in both the transmit and receive paths are programmable which allows adaptive HDSL to be performed also. The part is available in a 48-pin LQFP package and is specified for a temperature range of -40 oC to +85 oC.
FUNCTIONAL BLOCK DIAGRAM
V DR IV E T x-D E CO U P
T xD A T A T xS YN C T xC LK 1 4-B it D A C 6 P ole A da ptive B esse l Filte r PGA 0 dB -6 dB
L in e D rive r
D RV -O U T P D RV -O U T N
A DC C LK S CL K S DO DR C AP -T C AP -B R EF -CO M V RE F C M -L V L -6 dB -3 dB 0 dB +3 d B +6 d B A DC B uffer 4 P ole A da ptive B utterw orth Filter H YBIN-2 B H YBIN-2 A H YBIN-1 A H YBIN-1 B
1 2-B it A D C
PGA
H ybrid
S P IC LK T FS DT DR R ES E T B P W RD O W N B SPI C on trol/ C on figu ratio n
FILO U T P
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 World Wide Web Site: hppt://www.analog.com
FILO U T N
A DC IN N
A DC IN P
PRELIMINARY TECHNICAL DATA
AD5011-SPECIFICATIONS1
Parameter Min TRANSMITCHANNEL Signal to Noise2 Total Harmonic Distortion2 TRANSMIT DAC Resolution Clock Frequency Coding Output Update Rate3 Output Voltage TRANSMIT FILTER Cutoff Frequency4 68 66
(VDD = +3.15 V to +3.45 V; AGND = DGND = 0 V; TA = TMIN to TMAX unless otherwise noted)
AD5011B Typ Max 71 71 14 18.688 2s Complement 1168 1 49 - 120.8 108 - 265 235 - 580 +5 +10 +40 1.5 +100 13.5 4 2 +1 Units Test Conditions/Comments
dB dB Bits MHz kHz Vpp Diff kHz kHz kHz % % nom V mV dBm Vpp Diff Vpp Diff dB dB dB 5 Vpp Diff V kW mV dB dB dB kHz kHz kHz % % nom pF W Bits MHz V V mA pF
FOUT = 73 kHz FOUT = 73 kHz
Bottom Range (8 kHz steps) Mid Range (18 kHz steps) Top Range (40.5 kHz steps)
Corner Frequency Accuracy Adjacent Corner Step LINE DRIVER5 VCM Common Mode Voltage Error Output Power Output Voltage Channel Gain Accuracy RECEIVE CHANNEL Signal to (Noise + Distortion)6 Total Harmonic Distortion HYBRID INTERFACE Input Voltage Range Common Mode Input Voltage Input Impedance Input Offset Voltage PROGRAMMABLE GAIN AMPLIFIER7 Overall Gain Accuracy Gain Step Gain Step Accuracy RECEIVE FILTER Cutoff Frequency4 66 68
Tx-GAIN = 0 Tx-GAIN = 1
68 71
FIN = 73 kHz FIN = 73 kHz PGA = 0 dB
1.5 10 80 +1 3 +0.25 49 - 120.8 108 - 265 235 - 580 +5 +10 +40 20 TBD 12 2s Complement 2.32 2 3 0
PGA = 0 dB For all Gain Settings from -6 dB to +9 dB
Bottom Range (8 kHz steps) Mid Range (18 kHz steps) Top Range (40.5 kHz steps)
Accuracy Adjacent Corner Step Output Load Capacitance Output Load Resistance RECEIVE ADC Resolution Coding Sample Rate LOGIC INPUTS Input Logic High, VINH8 Input Logic Low, VINL IIN, Input Current CIN, Input Capacitance
0.2 +10 10 -2-
VIN = 0 V to DVDD
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PRELIMINARY TECHNICAL DATA AD5011
Parameter LOGIC OUTPUTS Output Logic High, VOH9 Output Logic Low, VOL POWER SUPPLIES AVDD, DVDD IDD Normal Mode (excluding Driver) Line Driver
1 2
AD7346B Min Typ VDD - 0.3
Units Max V V V mA mA
Test Conditions/Comments
0.3 3.15 3.3 32 75 3.45
IOUT = 200 mA IOUT = 200 mA
33 W Differential Load
Operating temperature range is as follows: B Version: -40C to +85C. The complete transmit path spectrum and pulse shape comply with ETSI requirements. SNR and THD are measured within a 547 kHz bandwidth. Noise and Spurious tones beyong 540 kHz are therefore excluded. 3 The transmit DAC maximum update rate is half the maximum output data rate i.e. 1168 kHz. The maximum transmit clock is 16 x 1168 = 18.688 MHz. 4 There are three ranges (bottom range, mid range, top range), each range being divided into eight steps. The transmit filter corner frequency can be set independently from the receive filter corner frequency. the filter tuning circuit requires a continuous 16.384 MHz clock applied to the Fclk pin. 5 Transformer turns ratio = 1:2:3 at 50 kHz when loaded by ETSI (RTR/TM3036) HDSL test loops. 6 With 547 kHz filter snd 0 dB PGA gain selected. 7 The PGA gain is set by setting the PGA-GC bits in the control register. 8 The input switching threshold voltage is approximately 1.2 V to allow interfacing to 2.5 V and 3.3 V logic. 9 The output level is determined by the voltage on the logic supply pin VDRIVE. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA AD5011 TIMING CHARACTERISTICS (V
Parameter Limit at TMIN to TMAX (B Version)
DD
= +2.7 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns min typ min typ min min min min typ min typ min min min
Test Conditions/Comments ADCCLK Rising Edge to SCLK Rising Edge Delay SCLK Rising Edge to ADCCLK Falling Edge Delay SCLK Period (1/32*ADCCLK Period) Data Setup Time Before SCLK Falling Edge Data Hold Time After SCLK Falling Edge ADCCLK Rising Edge to SCLK Rising Edge Delay SCLK Rising Edge to ADCCLK Falling Edge Delay SCLK Period (1/16*ADCCLK Period) Data Setup Time Before SCLK Falling Edge Data Hold Time After SCLK Falling Edge TxCLK Period (1/18.688 MHz) Data Setup Time Before TxCLK Rising Edge Data Hold Time After TxCLK Rising Edge TxSYNC Low Time TxCLK Rising Edge to TxSYNC Falling Edge Delay ns max SPICLK Period TFS Setup Time Before SPICLK Falling Edge TFS Hold Time After SPICLK Falling Edge TFS High Time DT Setup Time Before SPICLK Falling Edge DT Hold Time After SPICLK Falling Edge DR Setup Time Before SPICLK Falling Edge (R/W = 1) DR Hold Time After SPICLK Falling Edge (R/W = 1)
ADCCLK <= 1160kHz t1 1.5*t 3 2*t 3 t2 2.5*t 3 3*t 3 t3 26.939 t4 5 t5 10 1160 kHz < ADCCLK <= 2320 kHz t6 20 1*t 8 t7 1.5*t8 2*t 8 t8 26.939 t9 5 t10 10 TRANSMIT DAC t11 53.5 t12 12 t13 10 t14 t11 t15 3 CONTROL REGISTER t16 50 76 t17 15 t16 - 15 t18 15 t16 - 15 t19 t16 t20 7 t21 10 t22 7 t23 10
Guaranteed by design but not production tested.
ns min ns min ns min ns min ns min t11/2 ns ns ns ns ns ns ns ns ns ns ns min typ min max min max typ min min min min
t1
AD C CL K
t2
t3
S CL K
t4
S DO
t5
D0 D 11 D 10 D9
D 11
D 10
D1
SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges
Figure 1. ADC Timing (ADCCLK <= 1160 kHz)
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PRELIMINARY TECHNICAL DATA AD5011
t6
AD C CL K
t7
t8
S CL K
t9
S DO
t 10
D0 D 11 D0
D 11
D 10
D1
D 10
D1
D 11
D 10
D9
SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges
Figure 2. ADC Timing (1160 kHz < ADCCLK <= 2320 kHz)
t 15
T xC LK
t 14 t 13
T xS Y NC
t 12 t 11
T xD AT A
D 13
D 12
D 11
D2
D1
D0
X
X
D 13
D 12
The rising edge of TxSYNC can occur anywhere as long at the TxSYNC low time exceeds one TxCLK period. The TxSYNC falling edge must occur after the TxCLK rising edge which captures the LSB of the previous word. This ensures correct loading into the DAC. The first 14 bits are loaded into the DAC, the 2 LSBs being don't cares.
Figure 3. DAC Timing
t 16
S P ICL K
t 17 t 18
T FS
t 19 t 21 t 20
DT
R /W SEL2 SEL1 SEL0 D 11
D 10
D1
DO
t 23 t 22
DR (R/W = 1)
D 11
D 10
D1
DO
DR (R/W = 0
If R/W = 1, the selected register's contents will be output on DR. If R/W = 0, no data will be output on DR. The SEL bits identify which of the four register banks is being written to. The 12 LSBs contain the word. When the AD5011 is reset using RESETB, the registers are reset to zero.
Figure 4. Control Interface
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PRELIMINARY TECHNICAL DATA AD5011
PIN DESCRIPTION
Mnemonic POWER SUPPLY VDRIVE AGND AGND DVDD DGND
Function Digital output drive level. Analog power supply. Analog Ground. Positive power supply for the digital section. Digital Ground.
TRANSMIT CHANNEL TxDATA Transmit data input. TxSYNC Transmit data frame synchronization, logic input. TxCLK Transmit serial clock, logic input. TxDECOUP Transmit DAC reference decoupling pin. The reference which supplies the DAC needs some external decoupling. DRV-OUTP Differential line driver positive output. DRV-OUTN Differential line driver negative output. EXTERNAL INTERFACE SPICLK Serial interface clock, logic input. TFS Serial Interface frame synchronisation, logic input. DT Serial interface data input. DR Serial interface data output. RESETB Master Reset. This is an active low logic input. PWRDWNB Master powerdown. When PWRDWNB is taken low, the complete AD5011 device is placed in a sleep mode. FCLK Filter tuning clock. The clock for the filter tuning circuit in both the transmit and receive paths is supplied to FCLK. A 16.384 MHz should be connected to this pin to obtain the specified frequencies. TEST Test Mode. When TEST is tied to DVDD, the AD5011 is placed in a test mode. For normal operation, this pin should be tied to DGND. RECEIVE CHANNEL HYBIN-2B Hybrid non-inverting input. HYBIN-2A Hybrid inverting input. HYBIN-1B Hybrid inverting input. HYBIN-1A Hybrid non-inverting input. FILTOUTP Positive differential output of the antialiasing filter. FILTOUTN Negative differential output of the antialiasing filter. ADCINP Positive differential input to the ADC. ADCINN Negative differential input to the ADC. CAP-T Receive ADC reference decoupling pin. The reference which supplies the ADC needs some external decoupling. CAP-B Receive ADC reference decoupling pin. The reference which supplies the ADC needs some external decoupling. VREF Voltage Reference. The external reference is applied to this pin. REF-COM Reference common. COM-LVL Common mode level. ADCCLK ADC Sample clock, logic input. This clock also operates as the frame synchronization. SCLK ADC serial interface clock, logic input. SDO ADC serial data out.
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PRELIMINARY TECHNICAL DATA AD5011
Table 1. Control Register
Serial Register SEL[2:0]=000 Control Reg D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] R/W = 0 SEL[2] = 0 SEL[1] = 0 SEL[0] = 0 PWDN-Tx PWDN-Rx LOOPBACK AA-BUF-BP AA-FLTR-BP Tx-GAIN-SEL Tx-DACOUT Tx-LPF-BP Tx-DRVR-BP PGA-GC2 PGA-GC1 PGA-GC0
SEL[2:0]=001 Tx Prog Filt Reg R/W = 0 SEL[2] = 0 SEL[1] = 0 SEL[0] = 1 WRBOTH TPFD[10] TPFD[9] TFPD[8] TFPD[7] TFPD[6] TFPD[5] TFPD[4] TFPD[3] TFPD[2] TFPD[1] TFPD[0]
SEL[2:0]=010 Rx Prog Filt Reg R/W = 0 SEL[2] = 0 SEL[1] = 1 SEL[0] = 0 WRBOTH RPFD[10] RPFD[9] RPFD[8] RFPD[7] RFPD[6] RFPD[5] RFPD[4] RFPD[3] RFPD[2] RFPD[1] RFPD[0]
SEL[2:0]=011 Test Purposes Only R/W = 0 SEL[2] = 0 SEL[1] = 1 SEL[0] = 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Register Functions
Mnemonic R/W PWDN-Tx PWDN-Rx LOOPBACK AA-BUF-BP AA-FLTR-BP Tx-GAIN-SEL WRBOTH
Function When R/W is high, the register bank addressed by SEL[2:0] is loaded into the output shift register. Serial data will subsequently be output onto the DR pin. If R/W is low, the serial input data located at D[11:0] will be written into the register bank addressed by SEL[2:0]. When PWDN-Tx is low, the entire transmit channel is powered down. The line driver output is high impedance when the transmit channel is powered down. When this bit is low, the entire receive channel is powered down. When this bit is high, analog loopback is selected. When this bit equals 1, the ADC buffer is bypassed. When this bit equals 1, the receive filter is bypassed. When Tx-GAIN-SEL equals 1, the output of the transmit filter is attenuated by 6 dB. The transmit and receive programmable filter corner frequencies are addressed by the 11-bits words TPFD and RPFD respectively. TPFD data is loaded from the serial input register to the transmit filter register if SEL[2:0] = 010. RPFD data is written to the receive filter register if SEL[2:0] = 010. If WRBOTH equals 1 during either of the above conditions, the word in the serial input register is loaded into both the TFPD and RFPD registers.
Configuring the Transmit Channel
Tx-DACOUT Tx-FILT-BP 0 1 0 0 0 0 1 0
Tx-DRVR-BP 0 0 0 1
Configuration Default. All Components in the Tx channel are used. The DAC output is seen at the line driver output pins. The line driver amplifier output is in a high impedance state. The Tx filter is bypassed. The DACOUT is fed to the PGA. The filter amplifier output is in a high impedance state. The filter output is seen at the line driver output pins. The line driver amplifier output is in a high impedance state.
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PRELIMINARY TECHNICAL DATA AD5011
Programmable Gain Amplifier Gain Settings (Receive Signal)
GGA-GC2 0 0 0 0 1 1 1 1
PGA-GC1 0 0 1 1 0 0 1 1
PGA-GC0 0 1 0 1 0 1 0 1
Gain (dB) -6 -3 0 3 6 9 9 9
Transmit and Receive Filter Corner Frequency (kHz)
TPFD [7:0] RPFD[0:7] TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TPFD[8] RPFD[8] 49 52 59.8 67.5 75.3 83 90.8 98.5 106.3 114 120.8
TPFD[9] RPFD[9] 108 114 131 148 165 182 199 216 233 250 265
TPFD[10] RPFD[10] 235 250 287 324 361 399 436 473 510 547 580
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